The presence of RF circuitry on printed circuit boards (PCBs) was once limited to military and aerospace industry requirements. Now, the proliferation of the wireless handheld communications and remote-control devices is driving the need for mixed analog, digital and RF designs at a significantly increasing rate. Handhelds, base stations, remote controls, Bluetooth devices, computer wireless, many consumer devices, and mil/aero systems now all contain RF.
In the past, design functionality was performed (and repeated) in two design environments through non-intelligent ASCII interfaces (Figure 1). Both the PCB system design and the RF specialized design systems had their own libraries, RF design databases, and design archiving. It required that design data (schematic and layout) and libraries be managed (and synchronized) in both environments through the cumbersome ASCII interfaces.
RF simulators only simulate the ideal RF circuit. The actual implementation in the mixed system with fractioned ground planes, ground vias and neighboring RF circuitry has been extremely difficult to analyze and it's well known that these additional shapes will have a profound impact on the RF circuit operation.
This old methodology has been used successfully for years to design mixed-technology boards, but as the RF content in products increases, the problems with having two separate design systems is starting to impact designer productivity, time-to-market, and quality of the products.
With these issues in mind, Mentor Graphics has developed a dynamic link that integrates the PCB schematic and layout tool with RF design and simulation tools, resulting in a solution that overcomes the shortcomings of the classic RF design. Working with RF design experts, a set of requirements was identified and a new solution designed.
No integration — no matter how good — can help maintain design intent between PCB design and RF design unless there is a common understanding of the technology-specific environment between the tool sets. In other words, the typical layer-oriented structures in PCB layout has to be understood by the RF design tools and the parametric planar microwave elements used in the RF design environment must be understood by the PCB system.
Another key issue is that PCB systems regard RF shapes as short circuits and this prevents proper design rule checks (DRC) of the design. With today's complex RF system designs, functional RF aware DRC is a must to enable a correct by design methodology.
All these contribute to the design intent. Preserved design intent is critical as this is the foundation to support multiple iterative roundtrips of design data between tools without losing information.
RF design is an iterative process. A design is tweaked or optimized in many steps. It was difficult in the past to do this in the context of the real PCB design. When the optimized RF module was implemented on the PCB, there was no guarantee that it would still work in an optimal manner. As a validation, the PCB implementation was sent to electromagnetic field analysis (EM).
This design flow has several problems. First, the circuit is pushed to simulation as simple metal polygons, so there is no way to modify the metal in the RF tool and send the optimized result back to PCB design and still have an intelligent RF circuit. Second, EM solutions are time consuming so it may be best to wait until it's needed.
In the new flow, as the PCB and RF tools share an understanding of the design intent, the circuit can be looped back and forth between the tool sets multiple times without loss of design intent. This means that circuit simulation (which is very fast) and EM analysis (when needed) can be repeated and results can be compared for every change made to the circuit. This is done within the context of the real PCB with fractioned ground planes, RF shapes, traces, vias, and other components.
Libraries have always been a hurdle in RF system design. The standard components in the RF library (capacitors, resistors, transistors, etc.) frequently lack some of the parameters required for the PCB design and manufacturing processes. Likewise, the PCB design libraries usually don't contain the planar microwave elements used in the RF domain to build up RF circuitry.
In the past, a snapshot has been taken of the microwave element library, but as with any snapshot, it could be outdated in no time, forcing designers to manually ascertain that the PCB and microwave library is kept in absolute synchronization. And not just synchronized, but perfectly synchronized to ensure performance on the PCB is 100% identical to what you simulate. Obviously, as this process involved people, it failed now and then. The new integration solves this dilemma using an inter-tool dynamic link to synchronize the library.
Something different had to be developed and this led to a network-based inter-tool communication providing a dynamic two-way link between RF design and system-level PCB design (Figure 2). To support concurrent engineering processes, multiple board designers can operate simultaneously on the same design database and each link to one or multiple simulation sessions. Now an RF module can be designed in the RF design tool and, when appropriate, be pushed over and become an intelligently integrated part of the system-level schematic and PC board rather than the black box circuit of the past. At this stage, circuit updates can be made in either environment and the impact be simulated.
There are several well-known RF PCB design bottlenecks. First, as each RF module on a board may have been designed by a separate RF design team and the module may live its own life in terms of versioning, variants and reuse, it becomes vital to be able to manage the circuit as a group that can be managed as one entity and its origin and version be traced — but still be accessed as individual circuit elements at any time. To resolve this issue, the schematic and layout tools were expanded to support hierarchical circuit grouping. This way, even though an RF circuit is laid out on a PCB, it is still kept together as an RF circuit and can be linked to the proper RF team for analysis.
The next hurdle is ground plane clearance. In the classic design process, the RF metal was imported as a black box piece of metal and ground clearance was handcrafted as plane voids on every layer needed. When the RF circuit was updated — which was a frequent operation — the cutouts had to be manually edited to reflect the new circuit. This edit process alone can take weeks for some designs.
With a new design flow that promotes iterative updates between RF design and PCB design; manual updating is too slow. Instead, an intelligent parametric RF shape clearance is introduced to let the RF circuit clear ground the way the RF engineer defines it, and to have it parametrically updated as the RF circuit evolves during design, as shown in Figure 3. This parametric plane clearance cannot only be defined for the same layer on which the RF shape is placed, but also for layers above and below the shape, including the solder mask. If the RF circuit is updated with changed dimensions or if it's being moved to a new layer, these cutouts automatically update, saving a tremendous amount of cycle time.
Interconnection between RF elements on the PCB typically uses meander lines instead of normal PCB traces to connect RF circuits. These meander lines can have tapered width changes, optimal impedance miter, or curved bends.
In the past these were made as metal plane shapes and were difficult to edit. Furthermore, as they were metal polygons, the only way to simulate was to use a time-consuming EM solution. Mentor has solved this dilemma by designing a meander line design object for its PCB tools. This way, the PCB designer can connect RF signals effectively and when simulation is needed, the meander lines can be sent to EM analysis — as in the past — or automatically be decomposed into fast circuit models.
A striking feature of most RF system designs is the very large number of via holes stitched along RF shapes, around plane contours or peppered over plane surfaces.
This so-called via stitching is used to reduce radiation losses when stitched along RF shapes or when peppered across planes, to prevent parallel plane excitation.
Adding these vias manually costs countless hours or days and need manual rework each time the circuit is updated in design iteration. Many board designers developed smart scripts and programs to add the vias but the issue with rework is still unsolved.
Now, designers can automatically generate via patterns and contour stitching parametrically in elaborate patterns, multirow stitching along shapes, and include them in the EM simulation (Figure 3).
The new RF design paradigm has put RF design companies in a tricky situation with unacceptable cycle time and excessive design cycles. We are now working with RF tool vendors at a different level than what has been the norm in order to provide a design flow that is tailored to meet the challenges seen in the industry today and in the future.
The prime goal — to cut design cycles — is reached by ensuring a synchronized library and by facilitating a fast and easy integrated simulation flow. As designers can simulate frequently as the design evolves, the system can be validated up front. RF-aware DRC promoting correct by design also contributes.
Cycle time was traditionally wasted in cumbersome file translation between tools and in the fact that the PCB tools did not understand RF or even support some of the primary RF design requirements.
ASCII file transfer is a relic of the past. The demand for integrated design teams across technology and global boundaries dictates direct tool integration where the tool sets share an understanding of RF.