Objectives:
· We would like to design a simple Class A power amplifier using the loadpull method.
· This is a low power and low voltage power amplifier, the output is slated for not more than 10 mW, with operating frequency at 410 MHz.
· The design steps is divided into 3 parts, the first is to design the DC biasing of the amplifier, the second is to perform a loadpull test on the circuit and finally we verify the performance of the circuit. Two performance test is carried out, the gain compression test and the third order intercept (TOI) point test.
Background:
· The transistor chosen for the job is BFR 92A which comes in SOT23 package. The maximum I_{C} sustainable by the transistor is 30.0mA, with transistion frequency f_{T} = 5GHz, which is more than sufficient for the job.
· Since this is a large signal nonlinear circuit, substantial harmonics will be generated, therefore the chosen simulation method is the Harmonic Balance Method.
· Common emitter configuration is used and the schematic for performing DC simulation and large signal loadpull test is shown in Figure 1.
· The amplifier is driven by a source with impedance of 50Ohms at the fundamental frequency. We assume the source impedance also maintains at 50Ohms at the other higher harmonics. If this assumption is not true, then we just assign new values to the impedance at higher harmonics.
Step 1: DC Simulation and Maximum RF Output Power Estimation
In performing this simulation we merely deactivate the Harmonic Balance and Parameter Sweep control. The DC simulation results are:
V_{C}  V_{E}  V_{B}  I_{C} 
3.0V  0.338V  1.12V  3.34mA 
The result is reasonable, as V_{CC} = 3.0V, V_{E} of 0.1V_{CC} or higher will ensure adequate bias stability and prevent thermal runnaway. The dissipated DC power is:
P_{DC} = (2´3.0)´0.00334 = 20.04mW
The RF output power will not be higher than this level. The ideal efficiency of this ClassA circuit is 50%, assuming a realistic value of 33%, the RF output power will be no more than6.61mW for linear operation.
Step 2: Performing LoadPull Test
Figure 1 – The schematic of the Class A power amplifier.
The loadpull test:
As it name implies, the loadpull test is a brute force method to find the optimum load impedance. We actually change large signal load impedance from a small value (near 0) to a large value and calculate the power deliver to the load. A series of contours, known as isopower lines are then plotted on the Smith chart, representing the load reflection coefficients with similar output power level. At the optimum load impedance the power amplifier will deliver maximum power to the load. The optimum load for power amplifier is different from the maximum conjugate gain load for small signal amplifier. In power amplifier design, we are more concern with the maximum output power than the gain of the amplifier. The purpose of the power amplifier is to provide a buffer between the load and other amplifier stages, so that a slight change of load will have minimal effect on the performance of other small signal amplifier stages. In this respect we assume that there is adequate drive from the source for the power amplifier to operate at the peak power level. Some assumptions for this simulation:
· We only consider up to fifth harmonics in the Harmonic Balance simulation.
· The large signal source impedance remains at 50Ohms for all harmonics.
· The large signal load impedance appears as short circuit for higher harmonics (Due to non convergence during simulation, we set Z_{L(2nd harmonic)} to 2.0Ohms). This is justified by the fact that impedance matching network is usually used at the output. We could utilize a lowpass impedance matching network for this purpose. If this is not the case, then we must determine the relationship between the large signal impedance values at higher harmonics and the impedance value at the fundamental frequency. As during the loadpull test, we only change the impedance value at the fundamental frequency. This is a very complicated affair and will not be pursued at this state. As the aim is to clarified the concept and procedure of a ClassA power amplifier design.
Changing the load impedance:
To sweep the load impedance at fundamental frequency, we change its S_{11} amplitude ® and phase (q).
G_{Load }= S11 = Re^{j}^{q}
Thus it is seen in from “SweepVar” and “Parameter Sweep” settings in Figure 1, R is swept from 0 to 0.98 while q is swept from 0^{o} to 360^{o} at a step of 10^{o}.
Source power and harmonic distortion:
The source used is a onetone power source. As shown in Figure 1, this example use a source that delivers a power of –20dBm if a load of 50Ohm is connected to it. In other words P_{in} = 20dBm is the available power. Once we have determined the load impedance, we need to check for the level of harmonic distortion. This is done by calculating the ratio of power at fundamental frequency over power due to higher harmonics. The current probes and named nodes in the schematic of Figure 1 are for this purpose. We call this ratio the Distortion Ratio (DR). Whenever this ratio is less than 0.1 or –10dB, we can assume the circuit to be in linear mode. Concepts such as input impedance can then be applied. The ClassA power amplifier is essentially a linear power amplifier. From the theory of power amplifier[1], once nonlinear distortion sets in, the maximum power delivered at the fundamental frequency will cease to increase. Any increase in input power to the amplifier will be converted to power at the harmonics.
Determining the Optimum Load Impedance:
· Set the source power at a starting value, say –20dbm.
· Perform the loadpull test. Find load impedance for maximum output power.
· Check that DR < 0.05.
· Increase source power, say to –15dbm.
· Repeat the loadpull test. You should see that the new load impedance for maximum output power only changes slightly. Check that DR still less than 0.05.
· Increase source power further to –10dbm. Repeat loadpull test until DR > 0.05.
· The load impedance for maximum output power is the optimum load impedance.
Figure 2 – The loadpull test result when DR is just less than 0.05.
From Figure 2, a good power amplifier should have large isopower contour area. This signifies that the delivered output power is insensitive to load. The power amplifier can deliver considerable power to a wide range of load with little change in output power level from its maximum value. However this is usually difficult to fulfill. In Figure 2, the result is reasonable. The maximum power the power amplifier can supply without significant nonlinear distortion is 8.304dbm or 6.7mW.
Step 3: Measure the large signal input impedance and Performing Input Impedance Matching
Since ClassA power amplifier is almost linear, we can measure the input impedance when the output is terminated with optimum load. The schematic to do this is shown in Figure 3.
Figure 3 – The schematic for measuring input impedance at optimum condition.
The input impedance can be computed as:
Z_{in} = V_{in}[1]/(I_{in}[1]) = 10.302 – j10.491
The square brackets are used to access the fundamental harmonic terms. After obtaining Z_{in} we then proceed to match the source impedance of 50Ohms to Z_{in} using conjugate matching method. The L impedance transformation network is chosen and the matching circuit is shown in Figure 4.
Figure 4 – The input impedance matching circuit.
Step 4: Gain Compression Test
The complete circuit of the ClassA power amplifier is shown in Figure 5.1. The simulation settings in the schematic is also used to perform the gain compression test. Basically we sweep the source power level “Pin” linearly from –30dBm to 0dBm. From Figure 5.2, the 1dB gain compression occurs at available source power P_{in}:
Pin_{1dB Compression} = 16.55dBm
Also shown in Figure 5.2 are the time domain waveforms for input and output voltage/current Pin = 16.55dBm. Therefore we notice that the actual useful output is actually:
P_{out(1dB)} = +2.10dBm
The nominal power gain when output is terminated with optimum load is:
P_{gain(opt)} = 19.68dB
Figure 5.1 – The schematic for Gain Compression test.




Figure 5.2 – Gain compression test results.
Step 5: Third Order Intercept (TOI) Point Test
The schematic used for performing TOI is similar to the schematic of Figure 5.1. The only change is we are now performing Harmonic Balance simulation with two frequencies (or two tones). Therefore mixing components must be taken into account. The simulation control variable “MaxOrder” must be set to at least 3 to access the (2f_{1}f_{2}) and (2f_{2}f_{1}) frequencies components. Refer to the online help on ADS for further information. The source must provide two frequency components at f_{1} = 410MHz and f_{2}=411MHz respectively. Thus the 1tone power source is replaced with an Ntone power source. For the TOI test both source magnitude must be similar[2].
Figure 6.1– Schematic for performing TOI test.
From Figure 6.2, the third order intercept (TOI) point occurs at P_{in} = 9.487dBm.
Figure 6.2 – Result of TOI analysis.
Summary: Performance of the ClassA Power Amplifier
Power Supply Voltage  3.0V 
Operating Frequency  410MHz 
Source impedance  50 W 
Optimum Load Impedance  Z_{L(opt)} = 438.05 + j0 W 
Maximum Output Power with Negligible Harmonic Distortion.  P_{out(max)} = +8.304dBm 
Large Signal Input Impedance at Optimum Load.  Z_{in(opt)} = 10.302 – j10.491 W 
Power gain when input is conjugately matched to source and at Optimum Load.  19.68dB 
1dB Gain Compression Level for Available Source Power  16.55dBm 
Output Power at 1dB Gain Compression Level.  +2.10dBm 
TOI input level (for Available Source Power), for f_{1}=410MHz and f_{2}=411MHz.  9.49dBm 
TOI output level (P_{IP})  9.53 dBm 
Required Available Source Power to produce P_{out(max)} at output  0.5 dBm 
Appendixes – Agilent ADS Data Display Used (ADS 2000).
Data Display for LoadPull Test:
Data Display for Finding Large Signal Input Impedance:
Data Display for 1dB Gain Compression Test:
Data Display for TOI Test:
No hay comentarios:
Publicar un comentario